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1 features ? single 2.7v - 3.6v supply dual-interface architecture ?rapids ? serial interface: 40 mhz maximum clock frequency (spi modes 0 and 3 compatible for frequencies up to 33 mhz) ?rapid8 ? 8-bit interface: 20 mhz maximum clock frequency page program operation ? dedicated intelligent programming operation ? 16,384 pages (1,056 bytes/page) main memory automated page and block erase operations two 1056-byte sram data buffers ? allows receiving of data while reprogramming the flash array continuous read capability through entire array ? ideal for code shadowing applications low-power dissipation ? 10 ma active read current typical ? serial interface ? 12 ma active read current typical ? 8-bit interface ? 5 a cmos standby current typical hardware data protection security: 128-byte security register ? 64-byte user programmable space ? unique 64-byte device identifier 100,000 program/erase cycles per page typical data retention ? 10 years commercial and industrial temperature ranges description the at45db1282 is a 2.7-volt, dual-interface sequential access flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage 128-megabit 2.7-volt dual-interface dataflash ? at45db1282 preliminary ? note: *optional use ? see pin description text for connection information. pin configurations pin name function cs chip select sck/clk serial clock/clock si serial input so serial output i/o7 - i/o0 8-bit input/output wp hardware page write protect pin reset chip reset rdy/busy ready/busy ser/byte serial/8-bit interface control tsop top view: type 1 cbga top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 nc nc rdy/busy reset wp nc nc nc vcc gnd nc nc nc nc cs sck si* so* nc nc nc nc nc nc nc i/o7* i/o6* i/o5* i/o4* vccp* gndp* i/o3* i/o2* i/o1* i/o0* ser/byte* clk nc nc nc a b c d e f g h j 1 2345 nc i/o2 i/o1 i/o0 nc ser/byte sck/clk cs so gndp nc gnd rdy/busy si vccp i/o7 vcc wp reset nc i/o6 i/o5 i/o4 i/o3 nc rev. 2472c?dflsh?11/03
2 at45db1282 2472c?dflsh?11/03 applications. this device utilizes atmel?s e - stac ? multi-level cell (mlc) memory technology, which allows a single cell to store two bits of information delivering a very cost effective high density flash memory. the at45db1282 supports rapids serial interface and rapid8 8-bit interface. rapids serial interface is spi compatible for frequencies up to 33 mhz. the dual-interface allows a dedicated serial interface to be connected to a dsp and a dedicated 8-bit interface to be connected to a microcontroller or vice versa. however, the use of either interface is purely optional. its 138,412,032 bits of memory are organized as 16,384 pages of 1,056 bytes each. in addition to the 132- megabit main memory, the at45db1282 also contains two sram buffers of 1,056 bytes each. the buffers allow the receiving of data while a page in the main memory is being reprogrammed, as well as writing a continuous data stream. eeprom emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify- write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel interface, the dataflash uses either a rapids serial interface or a 8-bit rapid8 interface to sequentially access its data. the simple sequen- tial access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. the device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential. the device operates at clock frequencies up to 40 mhz with a typical active read current consumption of 10 ma. to allow for simple in-system reprogr ammability, the at45d b1282 does not require high input voltages for programming. the device operates from a single power supply, 2.7v to 3.6v, for both the program and read operations. the at45db1282 is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck), or an 8-bit interface consisting of the input/output pins (i/o7 - i/o0) and the clock pin (clk). all programming and erase cycles are self-timed. block diagram memory array to provide optimal flexibility, the memory array of the at45db1282 is divided into three levels of granularity comprising of sectors, blocks, and pages. the ?memory architec- ture diagram? illustrates the breakdown of each level and details the number of pages per sector and block. all program operations to the dataflash occur on a page by page basis. the erase operations can be performed at the block or page level. flash memory array page (1056 bytes) buffer 2 (1056 bytes) buffer 1 (1056 bytes) i/o interface sck/clk cs reset vcc gnd rdy/busy ser/byte wp so si i/o7 - i/o0
3 at45db1282 2472c?dflsh?11/03 memory architecture diagram device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in tables 1 through 4. a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, tog- gling the sck/clk pin controls the loading of the opcode and the desired buffer or main memory address location through either the si (serial input) pin or the 8-bit input pins (i/o7 - i/o0). all instructions, addresses, and data are transferred with the most signifi- cant bit (msb) first. buffer addressing is referenced in the datasheet using the terminology bfa10 - bfa0 to denote the 11 address bits required to designate a byte address within a buffer. main memory addressing is referenced using the terminology pa13 - pa0 and ba10 - ba0, where pa13 - pa0 denotes the 14 address bits required to designate a page address and ba10 - ba0 denotes the 11 address bits required to designate a byte address within the page. read commands by specifying the appropriate opcode, data can be read from the main memory or from either one of the two sram data buffers. the dataflash supports rapids and rapid8 protocols for mode 0 and mode 3. please refer to the ?detailed bit-level read timing? diagrams in this datasheet for details on the clock cycle sequences for each mode. continuous array read: by supplying an initial starting address for the main memory array, the continuous array read command can be ut ilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. to perform a continuous read, an opcode of e8h must be clocked into the device followed by four address bytes (which comprises 7 don?t care bits plus the 25-bit page and byte address s equence) and a series of don?t care clock cycles (24 if using the serial interface or 19 if using the 8-bit interface). the first 14 bits (pa13 - pa0) of the sector 0 = 8 pages 8,448 bytes (8k + 256) sector 1 = 248 pages 261,888 bytes (248k + 7,936) block = 8,448 bytes (8k + 256) 8 pages sector 0 sector 1 page = 1,056 bytes (1k + 32) page 0 page 1 page 6 page 7 page 8 page 9 page 16,382 page 16,383 block 0 page 14 page 15 page 16 page 17 page 18 block 1 sector architecture block architecture page architecture block 0 block 1 block 30 block 31 block 32 block 33 block 2046 block 2047 block 62 block 63 block 64 block 65 sector 2 sector 64 = 256 pages 270,336 bytes (256k + 8k) block 2 sector 2 = 256 pages 270,336 bytes (256k + 8k) sector 63 = 256 pages 270,336 bytes (256k + 8k) sector 3 = 256 pages 270,336 bytes (256k + 8k)
4 at45db1282 2472c?dflsh?11/03 25-bit address sequence specify which page of the main memory array to read, and the last 11 bits (ba10 - ba0) of the 25-bit address sequence specify the starting byte address within the page. the 24 or 19 don?t care clock cycles that follow the four address bytes are needed to initialize the read operation. following the don?t care clock cycles, additional clock pulses on the sck/clk pin will result in data being output on either the so (serial output) pin or the eight output pins (i/o7- i/o0). the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached during a continuous array read, the device will continue reading at the begin- ning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit (or byte if using the 8-bit interface mode) in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pins (so or i/o7-i/o0). the maximum sck/clk frequency allowable for the con- tinuous array read is defined by the f car specification. the continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged. main memory page read: a main memory page read allows the user to read data directly from any one of the 16384 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. to start a page read, an opcode of d2h must be clocked into the device followed by four address bytes (which comprise 7 don?t care bits plus the 25-bit page and byte address sequence) and a series of don?t care clock cycles (24 if using the serial interface or 19 if using the 8-bit inter- face). the first 14 bits (pa13 - pa0) of the 25-bit address sequence specify the page in main memory to be read, and the last 11 bits (ba10 - ba0) of the 25-bit address sequence specify the starting byte address within that page. the 24 or 19 don?t care clock cycles that follow the four address bytes are sent to initialize the read operation. following the don?t care bytes, additional pulses on sck/clk result in data being output on either the so (serial output) pin or the eight output pins (i/o7 - i/o0). the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. a low-to-high tran- sition on the cs pin will terminate the read operation and tri-state the output pins (so or i/o7 - i/o0). the maximum sck/clk frequency allowable for the main memory page read is defined by the f sck specification. the main memory page read bypasses both data buffers and leaves the contents of the buffers unchanged. buffer read: data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. with the serial interface, an opcode of d4h is used to read data from buffer 1, and an opcode of d6h is used to read data from buffer 2. likewise with the 8-bit interface an opcode of 54h is used to read data from buffer 1 and an opcode of 56h is used to read data from buffer 2. to perform a buffer read, the opcode must be clocked into the device followed by four address bytes com- prised of 21 don?t care bits and 11 buffer address bits (bfa10 - bfa0). following the four address bytes, additional don?t care bytes (one byte if using the serial interface or two bytes if using the 8-bit interface) must be clocked in to initialize the read operation. since the buffer size is 1056 bytes, 11 buffer address bits are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bytes, the don?t care bytes, and the reading of data. when the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. a low-to-high transition on the cs pin will terminate the read operation and tri-state the output pins (so or i/o7 - i/o0).
5 at45db1282 2472c?dflsh?11/03 program and erase commands buffer write: data can be clocked in from the input pins (si or i/o7 - i/o0) into either buffer 1 or buffer 2. to load data into either buffer, a 1-byte opcode, 84h for buffer 1 or 87h for buffer 2, must be clocked into the device, followed by four address bytes comprised of 21 don?t care bits and 11 buffer address bits (bfa10 - bfa0). the 11 buffer address bits specify the first byte in the buffer to be written. after the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to-high transition is detected on the cs pin. buffer to main memory page program: a previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. the pro- gramming time is selectable by the system through the use of different opcodes between a normal mode and a fast mode (the fast program option will consume more current). a 1-byte opcode, 88h for buffer 1 or 89h for buffer 2 (98h for buffer 1 fast pro- gram or 99h for buffer 2 fast program), must be clocked into the device followed by four address bytes consisting of 7 don?t care bits, 14 page address bits (pa13 - pa0) that specify the page in the main memory to be written and 11 don?t care bits. when a low-to- high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main mem- ory that is being programmed has been previously erased using one of the erase commands (page erase or block erase). the programming of the page is internally self- timed and should take place in a maximum time of t p for normal programming or t fp for fast programming. during this time, the status register and the rdy/busy pin will indi- cate that the part is busy. page erase: the page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program to be uti- lized at a later time. to perform a page erase, an opcode of 81h must be loaded into the device, followed by four address bytes comprised of 7 don?t care bits, 14 page address bits (pa13 - pa0) that specify the page in the main memory to be erased and 11 don?t care bits. when a low-to-high transition occurs on the cs pin, the part will erase the selected page (the erased state is a logical 1). the erase operation is internally self- timed and should take place in a maximum time of t pe . during this time, the status regis- ter and the rdy/busy pin will indicate that the part is busy. block erase: a block of eight pages can be erased at one time. this command is useful when large amounts of data has to be written into the device. this will avoid using multiple page erase commands. to perform a block erase, an opcode of 50h must be loaded into the device, followed by four address bytes comprised of 7 don?t care bits, 11 page address bits (pa13 -pa3) and 14 don?t care bits. the 11 page address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected block of eight pages. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the status register and the rdy/busy pin will indicate that the part is busy.
6 at45db1282 2472c?dflsh?11/03 additional commands main memory page to buffer transfer: a page of data can be transferred from the main memory to either buffer 1 or buffer 2. to start the operation, a 1-byte opcode, 53h for buffer 1 and 55h for buffer 2, must be clocked into the device, followed by four address bytes comprised of 7 don?t care bits, 14 page address bits (pa13- pa0), which specify the page in main memory that is to be transferred, and 11 don?t care bits. the cs pin must be low while toggling the sck/clk pin to load the opcode and the address bytes from the input pins (si or i/o7 - i/o0). the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read or the rdy/busy can be monitored to determine whether the transfer has been completed. main memory page to buffer compare: a page of data in main memory can be compared to the data in buffer 1 or buffer 2. to initiate the operation, a 1-byte opcode, 60h for buffer 1 and 61h for buffer 2, must be clocked into the device, followed by four address bytes consisting of 7 don?t care bits, 14 page address bits (pa13 - pa0) that specify the page in the main memory that is to be compared to the buffer, and 11 don?t care bits. the cs pin must be low while toggling the sck/clk pin to load the opcode and the address bytes from the input pins (si or i/o7 - i/o0). on the low-to-high transition of the cs pin, the 1056 bytes in the selected main memory page will be com- pared with the 1056 bytes in buffer 1 or buffer 2. during this time (t xfr ), the status register and the rdy/busy pin will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. status register read: the status register can be used to determine the device?s ready/busy status, the result of a main memory page to buffer compare operation, or the device density. to read the status register, an opcode must be loaded into the device. after the opcode and optional dummy byte(s) is clocked in, the 1-byte status register will be clocked out on the output pins (so or i/o7 - i/o0), starting with the next clock cycle. in case of serial interface, opcode d7h is followed with an optional dummy byte (8 clocks). for serial applications over 25 mhz, opcode must be always followed with a dummy byte. in case of applications with 8-bit interface, opcode d7h and two dummy clock cycles should be used. when using the serial interface, the data in the sta- tus register, starting with the msb (bit 7), will be clocked out on the so pin during the next eight clock cycles. block erase addressing pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 b lo ck 00000000000xxx 0 00000000001xxx 1 00000000010xxx 2 00000000011xxx 3 11111111100xxx2044 11111111101xxx2045 11111111110xxx2046 11111111111xxx2047
7 at45db1282 2472c?dflsh?11/03 the six most-significant bits of the status register will contain device information, while the remaining two least-significant bits are reserved for future use and will have unde- fined values. after the one byte of the status register has been clocked out, the sequence will repeat itself (as long as cs remains low and sck/clk is being toggled). the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the status register. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. since the data in the status register is constantly updated, the user must toggle sck/clk pin to check the ready/busy status. there are five operations that can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buffer to main memory page program, page erase and block erase. the result of the most recent main memory page to buffer compare operation is indi- cated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. the device density is indicated using bits 5, 4, 3, and 2 of the status register. for the at45db1282, the four bits are 0, 1, 0, 0. the decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of dataflash devices. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp0100xx
8 at45db1282 2472c?dflsh?11/03 manufacturer and device id read this instruction allows the user to read the manufacturer id, device id, and extended device information. this mode is only offered via the serial interface with clock frequencies up to 25 mhz. a 1-byte opcode, 9fh, must be clocked into the device while the cs pin is low. after the opcode is clocked in, the manufacturer id, 2 bytes of device id and extended device infor- mation will be clocked out on the so pin. the fourth byte of the sequence output is the extended device information string length byte. this byte is used to signify how many bytes of extended device information will be output. manufacturer and device id information note: based on jedec publication 106 (jep106), manufacturer id data can be comprised of any number of bytes. some manufacturers may have manufacturer id codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7fh. a system sh ould detect code 7fh as a ?continuation code? and continue to read manufacturer id bytes. the first non-7fh byte would signify the last byte of manufacturer id data. for atmel (and some other manufacturers), the manufacturer id data is comprised of only one byte. byte 1 ? manufacturer id hex value jedec assigned code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1fh 0 0 0 1 1 1 1 1 manufacturer id 1fh = atmel byte 2 ? device id (part 1) hex value family code density code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 family code 001 = dataflash 29h 0 0 1 0 1 0 0 1 density code 01001 = 128-mbit byte 3 ? device id (part 2) hex value mlc code product version code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mlc code 001 = 2-bit/cell technology 20h 0 0 1 0 0 0 0 0 product version 00000 = initial version byte 4 ? extended device information string length hex value byte count bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h 0 0 0 0 0 0 0 0 byte count 00h = 0 bytes of information 9fh manufacturer id byte n device id byte 1 device id byte 2 this information would only be output if the extended device information string length value was something other than 00h. extended device information string length extended device information byte x extended device information byte x + 1 cs 1fh 29h 20h 00h data data si so opcode each transition represents 8 bits
9 at45db1282 2472c?dflsh?11/03 security register the at45db1282 contains a specialized register that can be used for security purposes in system design. the security register is a unique 128-byte register that is divided into two portions. the first 64 bytes (byte 0 to byte 63) of this register are allocated as a one- time user programmable space. once these 64 bytes have been programmed, they should not be reprogrammed. the remaining 64 bytes of this register (byte 64 to byte 127) are factory programmed by atmel and will contain a unique number for each device. the factory programmed data is fixed and cannot be changed. the security register can be read by clocking in opcode 77h to the device followed by four address bytes (which are comprised of 21 don?t care bits plus 11 byte address bits) and a series of don?t care clock cycles (24 if using the serial interface and 19 if using the 8-bit interface). the security register read can be terminated by asserting cs low to high after the 128-byte security register has been read out. the continuation of clocking past that will result in indeterminate data on the output. see the opcode table on page 13 for this mode. to program the first 64 bytes of the security register, a two step sequence must be used. the first step requires that the user loads the desired data into buffer 1 by using the buffer 1 write operation (opcode 84h ? see buffer write description). the user should specify the starting buffer address as location zero and should write a full 64 bytes of information into the buffer. otherwise, the first 64 bytes of the buffer may contain data that was previously stored in the buffer. it is not necessary to fill the remain- ing 992 bytes (byte locations 64 through 1055) of the buffer with data. after the buffer 1 write operation has been completed, the security register can be subsequently pro- grammed by reselecting the device and clocking in opcode 9ah into the device followed by four don?t care bytes (32 clock cycles if using the serial interface and four clock cycles if using the 8-bit interface). after the final don?t care clock cycle has been completed, a low-to-high transition on the cs pin will cause the device to initiate an internally self-timed program operation in which the contents of buffer 1 will be pro- grammed into the security register. only the first 64 bytes of data in buffer 1 will be programmed into the security register; the remaining 992 bytes of the buffer will be ignored. the security register program operation should take place in a maximum time of t p . operation mode summary the modes described can be separated into two groups ? modes that make use of the flash memory array (group a) and modes that do not make use of the flash memory array (group b). group a modes consist of: 1. main memory page read 2. continuous array read 3. main memory page to buffer 1 (or 2) transfer 4. main memory page to buffer 1 (or 2) compare 5. buffer 1 (or 2) to main memory page program 6. page erase 7. block erase group b modes consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read
10 at45db1282 2472c?dflsh?11/03 if a group a mode is in progress (not fully completed), then another mode in group a should not be started. however, during this time in which a group a mode is in progress, modes in group b can be started, except the first two group a commands (memory array read commands). this gives the dataflash the ability to vi rtually accommodate a continuous data stream. while data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). see application note an-4 (?using atmel?s serial dataflash?) for more details. pin descriptions serial/8-bit interface control (ser/byte ): the dataflash may be config- ured to utilize either its serial port or 8-bit port through the use of the serial/8-bit control pin (ser/byte ). when the ser/byte pin is held high, the serial port (si and so) of the dataflash will be used for all data transfers, and the 8-bit port (i/o7 - i/o0) will be in a high impedance state. any data presented on the 8-bit port while ser/byte is held high will be ignored. when the ser/byte is held low, the 8-bit port will be used for all data transfers, and the so pin of the serial port will be in a high impedance state. while ser/byte is low, any data presented on the si pin will be ignored. switching between the serial port and 8-bit port should only be done while the cs pin is high and the device is not busy in an internally self-timed operation. the ser/byte pin is internally pulled high; therefore, if the 8-bit port is never to be used, then connection of the ser/byte pin is not necessary. in addition, if the ser/byte pin is not connected or if the ser/byte pin is always driven high externally, then the 8-bit input/output pins (i/o7-i/o0), the vccp pin, and the gndp pin should be treated as ?don?t connects?. serial input (si): the si pin is an input-only pin and is used to shift data serially into the device. the si pin is used for all data input, including opcodes and address sequences. if the ser/byte pin is always driven low, then the si pin should be a ?don?t connect?. serial output (so): the so pin is an output-only pin and is used to shift data seri- ally out from the device. if the ser/byte pin is always driven low, then the so pin should be a ?don?t connect?. 8-bit input/output (i/o7-i/o0): the i/o7-i/o0 pins are bidirectional and used to clock data into and out of the device. the i/o7-i/o0 pins are used for all data input, including opcodes and address sequences. the use of these pins is optional, and the pins should be treated as ?don?t connects? if the ser/byte pin is not connected or if the ser/byte pin is always driven high externally. serial clock/clock (sck/clk): the sck and clk pins are input-only pins and are used to control the flow of data to and from the dataflash. the sck and clk pins are used for serial and 8-bit interface respectively. data is always clocked into the device on the rising edge of sck/clk and clocked out of the device on the falling edge of sck/clk. chip select (cs ): the dataflash is selected when the cs pin is low. when the device is not selected, data will not be accepted on the input pins (si or i/o7-i/o0), and the output pins (so or i/o7-i/o0) will remain in a high impedance state. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition on the cs pin is required to end an operation. hardware page write protect: if the wp pin is held low, the first 256 pages (sectors 0 and 1) of the main memory cannot be reprogrammed. the only way to repro- gram the first 256 pages is to first drive the protect pin high and then use the program
11 at45db1282 2472c?dflsh?11/03 commands previously mentioned. if this pin and feature are not utilized it is recom- mended that the wp pin be driven high externally. reset : a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin and feature are not utilized it is recommended that the reset pin be driven high externally. ready/busy : this open drain output pin will be driven low when the device is busy in an internally self-timed operation. this pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during programming/erase operations, compare operations, and page-to-buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. 8-bit port supply voltage (vccp and gndp): the vccp and gndp pins are used to supply power for the 8-bit input/output pins (i/o7-i/o0). the vccp and gndp pins need to be used if the 8-bit port is to be utilized; however, these pins should be treated as ?don?t connects? if the ser/byte pin is not connected or if the ser/byte pin is always driven high externally. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to mode 3. in addition, the output pins (so or i/o7 - i/o0) will be in a high impedance state, and a high-to-low transition on the cs pin will be required to start a valid instruction. the mode (mode 3 or mode 0) will be automatically selected on every falling edge of cs by sampling the inactive clock state. after power is applied and v cc is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started. system considerations the rapids serial interface is controlled by the serial clock sck, serial input si and chip select cs pins. the sequential 8-bit rapid8 is controlled by the clock clk, 8 i/os and chip select cs pins. these signals must rise and fall monotonically and be free from noise. excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. the pc board traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. if necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. as system complexity continues to increase, voltage regulation is becoming more important. a key element of any voltage regulation scheme is its current sourcing capa- bility. like all flash memories, the peak current for dataflash occur during the programming and erase operation. the regulator needs to supply this peak current requirement. an under specified regulator can cause current starvation. besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption.
12 at45db1282 2472c?dflsh?11/03 note: 1. the security register program command utilizes data stored in buffer 1. therefore, this command must be used in conjunction with the buffer 1 write command. see the security register description for details. table 1. read commands command serial/8-bit opcode main memory page read both d2h continuous array read both e8h buffer 1 read serial d4h buffer 2 read serial d6h buffer 1 read 8-bit 54h buffer 2 read 8-bit 56h table 2. program and erase commands command serial/8-bit opcode buffer 1 write both 84h buffer 2 write both 87h buffer 1 to main memory page program both 88h buffer 1 to main memory page program, fast program both 98h buffer 2 to main memory page program both 89h buffer 2 to main memory page program, fast program both 99h page erase both 81h block erase both 50h table 3. additional commands command serial/8-bit opcode main memory page to buffer 1 transfer both 53h main memory page to buffer 2 transfer both 55h main memory page to buffer 1 compare both 60h main memory page to buffer 2 compare both 61h status register read both d7h manufacturer and device id read serial 9fh security register program (1) both 9ah security register read both 77h
13 at45db1282 2472c?dflsh?11/03 notes: p = page address bit b = byte/buffer address bit x = don?t care *the number with (*) is for 8-bit interface. table 4 . detailed bit-level addressing sequence opcode opcode address byte address byte address byte address byte additional don?t care bytes* 50h 01010000 xxxxxxxp pppppppp pp xxxxxx xxxxxxxx n/a 53h 01010011 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 54h 01010100 xxxxxxxx xxxxxxxx xxxxxbbb bbbbbbbb 2* 55h 01010101 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 56h 01010110 xxxxxxxx xxxxxxxx xxxxxbbb bbbbbbbb 2* 60h 01100000 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 61h 01100001 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 77h 01110111 xxxxxxxx xxxxxxxx xxxxxbbb bbbbbbbb 3 or 19* 81h 10000001 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 84h 10000100 xxxxxxxx xxxxxxxx xxxxxbbb bbbbbbbb n/a 87h 10000111 xxxxxxxx xxxxxxxx xxxxxbbb bbbbbbbb n/a 88h 10001000 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 89h 10001001 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 98h 10011000 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 99h 10011001 xxxxxxxp pppppppp pppppx x x xxxxxxxx n/a 9ah 10011010 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx n/a 9fh 10011111 n/a n/a n/a n/a n/a d2h 11010010 xxxxxxxp pppppppp pppppbbb bbbbbbbb 3 or 19* d4h 11010100 xxxxxxxx xxxxxxxx xxxxxbbb bbbbbbbb 1 d6h 11010110 xxxxxxxx xxxxxxxx xxxxxbbb bbbbbbbb 1 d7h 11010111 n/a n/a n/a n/a 1/0 or 1* e8h 11101000 xxxxxxxp pppppppp pppppbbb bbbbbbbb 3 or 19* pa 1 3 pa 1 2 pa 1 1 pa 10 pa 9 pa 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 ba10 ba9 ba8 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0
14 at45db1282 2472c?dflsh?11/03 note: 1. after power is applied and v cc is at the minimum specified datasheet value, the system should wait 20 ms before an opera- tional mode is started. notes: 1. i cc1 during a buffer read is 25 ma maximum. 2. i cc2 during a buffer read is 25 ma maximum. absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v dc and ac operating range at45db1282 operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.6v dc characteristics symbol parameter condition min typ max units i sb standby current cs , reset , wp = v ih , all inputs at cmos levels 515a i cc1 (1) active current, read operation, serial interface f = 20 mhz; i out = 0 ma; v cc = 3.6v 10 20 ma i cc2 (2) active current, read operation, 8-bit interface f = 10 mhz; i out = 0 ma; v cc = 3.6v 12 20 ma i cc3 active current, program operation, page program v cc = 3.6v 50 ma i cc4 active current, program operation, fast page program v cc = 3.6v 65 ma i cc5 active current, page erase operation v cc = 3.6v 50 ma i cc6 active current, block erase operation v cc = 3.6v 50 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
15 at45db1282 2472c?dflsh?11/03 ac characteristics ? rapids serial interface symbol parameter min typ max units f sck sck frequency 40 mhz f car sck frequency for continuous array read 40 mhz t wh sck high time 9 ns t wl sck low time 9 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 150 ns t su data in setup time 5 ns t h data in hold time 7 ns t ho output hold time 2 ns t dis output disable time 10 ns t v output valid 10 ns t xfr page to buffer transfer/compare time 500 s t p page programming time 50 ms t fp fast page programming time 15 ms t pe page erase time 25 ms t be block erase time 50 ms t rst reset pulse width 10 s t rec reset recovery time 1 s
16 at45db1282 2472c?dflsh?11/03 input test waveforms and measurement levels t r , t f < 2 ns (10% to 90%) output test load ac characteristics ? rapid8 8-bit interface symbol parameter min typ max units f sck1 clk frequency 20 mhz f car1 clk frequency for continuous array read 20 mhz t wh clk high time 16 ns t wl clk low time 16 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 150 ns t su data in setup time 10 ns t h data in hold time 10 ns t ho output hold time 3 ns t dis output disable time 15 ns t v output valid 15 ns t xfr page to buffer transfer/compare time 500 s t p page programming time 50 ms t fp fast page programming time 15 ms t pe page erase time 25 ms t be block erase time 50 ms t rst reset pulse width 10 s t rec reset recovery time 1 s ac driving levels ac measurement level 0.45v 1.5v 2.4v device under test 30 pf
17 at45db1282 2472c?dflsh?11/03 ac waveforms six different timing waveforms are shown below. waveform 1 shows the sck/clk sig- nal being low when cs makes a high-to-low transition, and waveform 2 shows the sck/clk signal being high when cs makes a high-to-low transition. in both cases, out- put so becomes valid while the sck/clk signal is still low (sck/clk low time is specified as t wl ). timing waveforms 1 and 2 conform to rapids serial interface but for frequencies up to 33 mhz. waveforms 1 and 2 are compatible with spi mode 0 and spi mode 3, respectively. waveform 3 and waveform 4 illustrate general timing diagram for rapids serial inter- face. these are similar to waveform 1 and waveform 2, except that output so is not restricted to become valid during the t wl period. these timing waveforms are valid over the full frequency range (maximum frequency = 40 mhz) of the rapids serial case. waveform 5 and waveform 6 are for 8-bit rapid8 interface over the full frequency range of operation (maximum frequency = 20 mhz). waveform 1 ? spi mode 0 compatible (for frequencies up to 33 mhz) waveform 2 ? spi mode 3 compatible (for frequencies up to 33 mhz) cs sck/clk si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck/clk so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si
18 at45db1282 2472c?dflsh?11/03 waveform 3 ? rapids mode 0 (for all frequencies) waveform 4 ? rapids mode 3 (for all frequencies) waveform 5 ? rapid8 mode 0 (f max = 20 mhz) waveform 6 ? rapid8 mode 3 (f max = 20 mhz) cs sck/clk si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck/clk so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance si cs sck/clk i/o7 - i/o0 (input) i/o7 - i/o0 (output) t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck/clk i/o7 - i/o0 (output) t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance i/o7 - i/o0 (input)
19 at45db1282 2472c?dflsh?11/03 reset timing note: the cs signal should be in the high state before the reset signal is deasserted. command sequence for read/write operations (except status register read, manufacturer and device id read) write operations the following block diagram and waveforms illustrate the various write sequences available. cs sck/clk reset so or i/o7 - i/o0 (output) high impedance high impedance si or i/o7 - i/o0 (input) t rst t rec t css si or i/o7 - i/o0 (input) cmd 8 bits 8 bits 8 bits msb 7 bits don't care page address (pa13 - pa0) x x x x x x x x x x x x x x x x lsb x x x x x x x x 8 bits x x x x x x x x byte/buffer address (ba10 - ba0/bfa10 - bfa0) flash memory array page (1056 bytes) buffer 2 (1056 bytes) buffer 1 (1056 bytes) i/o interface si buffer 1 to main memory page program buffer 2 to main memory page program buffer 1 write buffer 2 write i/o7 - i/o0
20 at45db1282 2472c?dflsh?11/03 buffer write buffer to main memory page program (data from buffer programmed into flash page) read operations the following block diagram and waveforms illustrate the various read sequences available. si or i/o7 - i/o0 (input) cmd x xx, bfa10-8 bfa7-0 n n+1 last byte completes writing into selected buffer cs x si or i/o7 - i/o0 (input) cmd xxxxxxx pa13 pa12-5 cs starts self-timed erase/program operation xx pa4-0, xxx each transition represents 8 bits flash memory array page (1056 bytes) buffer 2 (1056 bytes) buffer 1 (1056 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so i/o7 - i/o0 n = 1st byte n+1 = 2nd byte
21 at45db1282 2472c?dflsh?11/03 main memory page read main memory page to buffer transfer (data from flash page read into buffer) buffer read si or i/o7 - i/o0 (input) cmd xxx...pa13 pa12-5 ba7-0 x x cs n n+1 so or i/o7 - i/o0 (output) pa4-0, ba10-8 24 cycles for serial 19 cycles for parallel starts reading page data into buffer si or i/o7 - i/o0 (input) cmd xx...pa13 pa12-5 x cs so or i/o7 - i/o0 (output) pa4-0, xxx i/o7-i/o0 (input) cmd x xx, bfa10-8 bfa7-0 cs n n+1 i/o7-i/o0 (output) x addr addr x 1 dummy byte (serial) 2 dummy bytes (parallel) each transition represents 8 bits n = 1st byte read n+1 = 2nd byte read
22 at45db1282 2472c?dflsh?11/03 detailed bit-level read timing ? rapids serial interface mode 0 continuous array read (opcode: e8h) main memory page read (opcode: d2h) si 1 1xxx cs so sck 12 62 63 64 65 66 67 high impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 8,447 of page n lsb msb t su t v si 1 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high impedance command opcode t su d 7 d 6 d 5 data out msb t v d 4
23 at45db1282 2472c?dflsh?11/03 detailed bit-level read timing ? rapids serial interface mode 0 (continued) buffer read (opcode: d4h or d6h) status register read (opcode: d7h) manufacturer and device id read (opcode: 9fh) si 1 1 0 10 xxx cs so sck 12345 44 45 46 47 48 49 50 51 xx high impedance command opcode t su d 7 d 6 d 5 data out msb t v d 4 si 1 1 0 10 111 cs so sck 12345 78910 11 12 15 16 high impedance status register output command opcode msb t su 6 d 1 d 0 d 7 lsb msb d 7 d 6 d 5 t v d 4 t v don?t care for freq. over 25 mhz si 1 0- 0 11 111 cs so sck 12345 78910 11 12 16 17 high impedance product id output command opcode msb t su 6 100 msb lsb 000 t v 1
24 at45db1282 2472c?dflsh?11/03 detailed bit-level read timing ? rapids serial interface mode 3 continuous array read (opcode: e8h) main memory page read (opcode: d2h) si 1 1xxx cs so sck 12 63 64 65 66 67 high impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 8,447 of page n lsb msb t su t v data out si 1 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68
25 at45db1282 2472c?dflsh?11/03 detailed bit-level read timing ? rapids serial interface mode 3 (continued) buffer read (opcode: d4h or d6h) status register read (opcode: d7h) manufacturer and device id read (opcode: 9fh) si 1 1 0 10 xxx cs so sck 12345 45 46 47 48 49 50 51 xx high impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 52 si 1 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6 t v don?t care for freq. over 25 mhz si 1 0 0 11 111 cs so sck 12345 78910 11 12 17 18 high impedance 000 product id output command opcode msb t su t v 6 110 lsb msb 0
26 at45db1282 2472c?dflsh?11/03 detailed 8-bit read timing ? rapid8 mode 0 continuous array read (opcode: e8h) main memory page read (opcode: d2h) i/o7-i/o0 (input) cmd addr xxx cs i/o7-i/o0 (output) clk 12 22 23 24 25 26 27 high impedance data data data data data data data data data data out byte 0 of page n+1 byte 1055 of page n t su t v i/o7-i/o0 (input) cmd addr addr addr addr xxx cs i/o7-i/o0 (output) clk 12345 20 21 22 23 24 25 26 27 xx high impedance data data data data out command opcode t su t v data
27 at45db1282 2472c?dflsh?11/03 detailed 8-bit timing ? rapid8 mode 0 (continued) buffer read (opcode: 54h or 56h) status register read (opcode: d7h) i/o7-i/o0 (input) cmd x x addr cs i/o7-i/o0 (output) clk 12345 8 high impedance command opcode t su t v data out data data data msb 7 6 addr x x i/o7-i/o0 (input) cmd cs i/o7-i/o0 (output) clk 12 3 high impedance t su x x data t v data data status register output
28 at45db1282 2472c?dflsh?11/03 detailed 8-bit read timing ? rapid8 mode 3 continuous array read (opcode: e8h) main memory page read (opcode: d2h) i/o7-i/o0 (input) cmd addr xxx cs i/o7-i/o0 (output) clk 12 23 24 25 26 27 high impedance data data data data data data data data data byte 0 of page n+1 byte 1055 of page n t su t v data out i/07-i/o0 (input) cmd addr addr addr addr xxx cs i/07-i/o0 (output) clk 12345 21 22 23 24 25 26 27 xx high impedance data data data data out command opcode t su t v data 28
29 at45db1282 2472c?dflsh?11/03 detailed 8-bit read timing ? rapid8 mode 3 (continued) buffer read (opcode: 54h or 56h) status register read (opcode: d7h) i/o7-i/o0 (input) cmd x x addr addr cs i/o7-i/o0 (output) clk 12345 68 79 high impedance data data data data out t su t v 10 x x i/o7-i/o0 (input) cmd cs i/o7-i/o0 (output) clk 1 23 high impedance x x data status register output t su t v data
30 at45db1282 2472c?dflsh?11/03 figure 1. algorithm for programming or reprogramming of the entire array sequentially notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page. 2. a page is written using a buffer 1 or buffer 2 write operation followed by a buffer (1 to 2) to main memory page program operation (either regularly or in fast program). 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start end provide address and data buffer write (84h, 87h) buffer to main memory page program (88h, 89h) or (98h, 99h) page erase (81h)
31 at45db1282 2472c?dflsh?11/03 figure 2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash sector must be updated/rewritten at least once within every 2,000 cumulative page erase/program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 2,000 cumulative page erase/program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using atmel?s serial dataflash?) for more details. buffer write (84h, 87h) page erase (81h) buffer to main memory page program (88h, 89h) or (98h, 99h) start main memory page to buffer transfer (53h, 55h) provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array increment page address pointer (2) end sector addressing pa1 3 pa1 2 pa1 1 pa1 0 pa 9 pa 8 pa 7 pa 6 pa5 pa4 pa3 pa2 - pa0 sec tor 00000000000 x 0 000000 xxxxx x 1 000001 xxxxx x 2 000010 xxxxx x 3 111100 xxxxx x 61 111101 xxxxx x 62 111110 xxxxx x 63 111111 xxxxx x 64
32 at45db1282 2472c?dflsh?11/03 note: 1. rapids serial interface. ordering information f sck (mhz) i cc (ma) ordering code package operation range active standby 40 (1) 20 (1) 0.015 at45db1282-tc 40t commercial (0 c to 70 c) 40 (1) 20 (1) 0.015 at45db1282-ti 40t industrial (-40 c to 85 c) 40 (1) 20 (1) 0.015 at45db1282-cc 44c2 commercial (0 c to 70 c) 40 (1) 20 (1) 0.015 AT45DB1282-CI 44c2 industrial (-40 c to 85 c) package type 40t 40-lead, (10 x 20 mm) plastic thin small outline package, type i (tsop) 44c2 44-ball, (8 x 12 mm) plastic chip-size ball grid array package (cbga)
33 at45db1282 2472c?dflsh?11/03 packaging information 40t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40t , 40-lead (10 x 20 mm package) plastic thin small outline package, type i (tsop) b 40t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation cd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 9.90 10.00 10.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
34 at45db1282 2472c?dflsh?11/03 44c2 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44c2 , 44-ball (5 x 9 array), 8 x 12 x 1.2 mm body, 0.4 mm ball plastic chip-scale ball grid array package (cbga) a 44c2 06/10/03 side view top view bottom view a b c d e f g h j 1 2 3 4 5 2.00 ref 2.00 ref marked a1 identifier d e d1 e1 e e ?b a a1 0.12 seating plane c c a1 ball corner common dimensions (unit of measure = mm) symbol min nom max note a ? ? 1.20 a1 0.25 ? ? d 7.90 8.00 8.10 d1 4.00 typ e 11.90 12.00 12.10 e1 8.00 typ e 1.00 typ ? b 0.40 typ
printed on recycled paper. 2472c?dflsh?11/03 /xm disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof, and dataflash ? are the registered trademarks, and rap- ids ? , rapid8 ? and e - stac ? are the trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trade- marks of others.

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